Interactive RISC-V Debugger
Write, execute, and analyze your assembly code step by step
Execution Logs
Register Bank
Symbolic Labels & Branching
Labels (e.g. 'loop:') are processed during assembly parsing to build the symbol table, but branch and jump instructions are not supported by this educational sequential interpreter. All control flow instructions must be executed step-by-step manually.
Low-Level Assembly Code Debugging
An architecture-level debugger is an essential tool for software development close to the hardware. It allows for step-by-step instruction execution, inspecting how data flows through CPU registers and memory on each clock cycle.
In the RISC-V architecture (RV32I), monitoring the 32-register bank and the Program Counter is key to understanding control flow, conditional branches, and memory manipulation. This interactive simulator lets you write code and visualize its impact on the machine in real-time without needing physical hardware boards.