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Interactive RISC-V Debugger

Write, execute, and analyze your assembly code step by step

PC INDEX: 0HEX: 0x0000

Register Bank

x0(zero)
0
x1(ra)
0
x2(sp)
0
x3(gp)
0
x4(tp)
0
x5(t0)
0
x6(t1)
0
x7(t2)
0
x8(s0/fp)
0
x9(s1)
0
x10(a0)
0
x11(a1)
0
x12(a2)
0
x13(a3)
0
x14(a4)
0
x15(a5)
0
x16(a6)
0
x17(a7)
0
x18(s2)
0
x19(s3)
0
x20(s4)
0
x21(s5)
0
x22(s6)
0
x23(s7)
0
x24(s8)
0
x25(s9)
0
x26(s10)
0
x27(s11)
0
x28(t3)
0
x29(t4)
0
x30(t5)
0
x31(t6)
0

Low-Level Assembly Code Debugging

An architecture-level debugger is an essential tool for software development close to the hardware. It allows for step-by-step instruction execution, inspecting how data flows through CPU registers and memory on each clock cycle.

In the RISC-V architecture (RV32I), monitoring the 32-register bank and the Program Counter is key to understanding control flow, conditional branches, and memory manipulation. This interactive simulator lets you write code and visualize its impact on the machine in real-time without needing physical hardware boards.