RISC-V · Computer architecture · Digital logic
Learn computer engineering by doing
SmartEng Tools combines explanations, worked examples, checked exercises and interactive simulators so you understand how a RISC-V instruction is encoded, executed and pipelined, and how the circuit that computes it is simplified.
Learning paths
- 1Guide: decoding an instruction
- 2Guide: from machine code to assembly
- 3Decoder and debugger
- 49 exercises
- 1Guide: the 5-stage pipeline
- 2Guide: RAW hazards and forwarding
- 3Pipeline simulator
- 43 exercises
- 1Guide: Karnaugh maps
- 2Guide: 7-segment decoder
- 3Karnaugh minimizer
- 44 exercises
How learning works here
Every topic follows the same sequence: concept → example → exercise → tool → verification. This is how it looks with a real case:
- 1. Concept
In RV32I, the formats that have a destination register (R, I, U and J) place rd in bits 11–7. S and B have no rd: those bits are part of the immediate.
- 2. Example
0x00500513 → bits 11–7 = 01010 = x10 (a0). The instruction is addi a0, zero, 5.
- 3. Exercise
What is the rd of 0x40B50533? Type your answer and check it.
- 4. Tool
The decoder colours the fields of any word you type.
- 5. Verification
Your answer is checked by the decoder’s own code, so it cannot contradict it.
Interactive tools
Each tool sits inside a lesson that explains what it models, how to read the result and what it does not do.
Guides
All guides- How to decode an RV32I instructionA five-step method and one example of each format (R, I, S, B, U and J), with how immediates are rebuilt and the most common mistakes.
- From machine code to assemblyWe turn an eight-word dump into a readable routine: decode, turn offsets into labels, recognize pseudo-instructions and work out what it does.
- How a 5-stage pipeline worksLatency versus throughput, how many cycles a sequence takes, why the real speedup is smaller than the number of stages and what breaks the ideal rhythm.
- RAW hazards, forwarding and stallsWhen a dependency forces a wait, which forwarding paths solve it, why load-use always costs a cycle and how reordering avoids it.
- How Karnaugh maps workWhy Gray order makes simplification possible, the grouping rules, essential prime implicants, functions with two solutions and how to get a product of sums.
- Designing a BCD to 7-segment decoderSeven four-variable functions with don’t cares: truth table, the map for segment e, minimal expressions for every segment and shared products.
Exercises
All 16 exercisesConcrete problems checked in your browser with the same algorithm as the corresponding tool. For example:
- Decode an R-type instruction — Identify the fields of 0x40B50533. Pay attention to funct7: it is what tells add and sub apart.
- Count the cycles of a load-use hazard — In the simulator’s 5-stage pipeline, how many cycles does this sequence take with and without forwarding? How many bubbles are there with forwarding?
- Minimize using don’t cares — Write a minimal sum of products for F(A,B,C,D) = Σm(1, 3, 7, 11, 15) + d(0, 2, 5). Use A, B, C, D and an apostrophe for NOT (for example A'B).
- Follow a loop — What is a0 when the loop exits? How many instructions run in total (counting every iteration)?
Student tools
- Final exam score calculator — the score you need in the final given your partial grades.
- ECTS average calculator — transcript average weighted by credits.
About SmartEng Tools
It is a personal, independent educational project, aimed at students of computer architecture and digital electronics courses. The tools run in your browser, are free and need no sign-up. Each one documents which algorithm it uses and what its limitations are.