Computer engineering: from instructions to logic gates

1. The ISA: a contract between software and hardware

The instruction set architecture (ISA) defines which instructions exist, what each one does and how it is encoded in bits. RISC-V is an open ISA; its 32-bit integer base, RV32I, has 40 instructions, each 32 bits wide. Take add a2, a0, a1: the specification says it adds registers a0 and a1 and puts the result in a2, and that it is encoded as the word 0x00B50633.

2. Decode: read the fields of the word

Hardware does not “read” text: it splits the word into fixed-position fields. The low 7 bits (opcode) say it is a register-register operation (R format); funct3 and funct7 select addition; and three 5-bit fields give the register numbers. This is the breakdown produced by the site’s decoder:

You can repeat it with any word in the RISC-V decoder.

3. Execute: change the processor state

Executing the instruction means applying its effect to the visible state: the 32 registers and the program counter (PC). If we first load a0 = 5 and a1 = 7, after add register a2 holds 12 and the PC moves on by 4 bytes.

addi a0, zero, 5
addi a1, zero, 7
add  a2, a0, a1

The RISC-V debugger runs this program one instruction at a time and highlights the register that changes at each step.

4. Pipeline: overlap instructions in time

A pipelined processor splits each instruction into stages (IF, ID, EX, MEM, WB) and starts a new one every cycle. The problem appears when an instruction needs a result the previous one has not written yet. In the program above, add needs a1 right after it is computed: without forwarding the simulator makes it wait 3 cycles (10 cycles in total); with forwarding the value is passed on from the next stage and there is no wait (7 cycles).

Check it in the pipeline simulator by switching forwarding on and off.

5. Digital logic: the circuit that adds

The addition is done by the ALU, which is built from logic gates. A 32-bit adder chains 1-bit full adders; each takes A, B and the carry-in C and produces a carry-out that is 1 when at least two inputs are 1. On a Karnaugh map that function occupies cells 3, 5, 6 and 7:

The three groups of two cells give Cout = BC + AC + AB: three 2-input AND gates and one 3-input OR, instead of the four 3-variable products of the truth table. Open it in the Karnaugh minimizer.

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