Digital logic path

Digital logic: from truth table to circuit

Designing a combinational circuit means going from a problem statement to a Boolean expression and from there to gates. The Karnaugh map is the tool that turns a truth table into a small expression. We use a concrete problem: detecting whether a 4-bit number is prime.

1. From problem statement to truth table

The input is a number N = ABCD between 0 and 15 (A is the most significant bit) and the output F is 1 if N is prime. The primes in that range are 2, 3, 5, 7, 11 and 13, so the function is written as a sum of minterms:

F(A,B,C,D) = Σm(2, 3, 5, 7, 11, 13)
N0123456789101112131415
ABCD0000000100100011010001010110011110001001101010111100110111101111
F0011010100010100

Written as is, as a sum of the six minterms, the function needs six 4-input AND gates and one 6-input OR. Simplifying means finding an equivalent expression with fewer terms and fewer literals.

2. From map to groups

On the map, rows are AB and columns are CD, in Gray order (00, 01, 11, 10): between two neighbouring cells only one bit changes, even from one edge to the opposite one. Each rectangular group of 2, 4 or 8 ones removes the variables that change inside the group.

AB \ CD00011110
0000011312
0104151706
11012113015014
100809111010
Groups: m2–m3, m3–m11, m5–m13 and m3–m7
  • m2 can only be grouped with m3: A'B'C.
  • m11 only with m3 (same column, rows 00 and 10, which touch across the edge): B'CD.
  • m13 only with m5: BC'D.
  • m7 can go with m3 (A'CD) or with m5 (A'BD). Both options are equally good.
F = A'B'C + B'CD + BC'D + A'CD

Four terms of 3 literals. The first three are essential prime implicants (they cover a 1 that no other group covers); the fourth is chosen between two candidates. The minimizer reaches the same expression.

3. Don’t cares change the result

Now suppose the input is a BCD digit: values 10 to 15 never occur. Those combinations are don’t cares (X): we can treat them as 1 whenever it helps to enlarge groups. 11 and 13 stop mattering and the function becomes Σm(2, 3, 5, 7) + d(10…15):

AB \ CD00011110
0000011312
0104151706
11X12X13X15X14
100809X11X10
Two 4-cell groups using don’t cares
F = B'C + BD

From four 3-literal terms to two 2-literal terms. Check it in the tool.

4. From expression to circuit

A sum of products is implemented in two levels: one AND gate per term and an OR joining them (or, equivalently, two levels of NAND). Counting terms and literals means counting gates and inputs:

VersionAND gatesORLiterals
Minterms (0–15)6 × 4 inputs1 × 624
Minimized (0–15)4 × 31 × 412
Minimized (BCD)2 × 21 × 24

The minimizer draws this AND-OR circuit below the result and, if you define several outputs, marks the products they share.

Suggested path

  1. Guide: how Karnaugh maps work — Gray order, adjacency, prime implicants and cases with several solutions.
  2. Exercises: placing minterms, adjacency, minimizing with don’t cares and checking a solution.
  3. Guide: BCD to 7-segment decoder, a complete design with seven outputs.

References

  • M. Karnaugh, “The Map Method for Synthesis of Combinational Logic Circuits”, Transactions of the AIEE, Part I, vol. 72, no. 5, 1953 — original paper describing the map method
  • E. J. McCluskey, “Minimization of Boolean Functions”, Bell System Technical Journal, vol. 35, no. 6, 1956 — tabular method the minimizer uses to find prime implicants
  • S. L. Harris, D. Harris — Digital Design and Computer Architecture: RISC-V Edition (Morgan Kaufmann) — combinational logic, Karnaugh maps, 7-segment decoder and RISC-V microarchitecture