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RISC-V · Encoding

Decoding an RV32I instruction

A RISC-V instruction is a 32-bit word. Encoding it means spreading its information (which operation, which registers, which constant) over fixed-position fields; decoding it is the reverse. Here you first do it by hand with an example and then with the tool.

What encoding an instruction means

The text addi a0, zero, 5 is for people. The processor only sees bits, so the ISA defines a template: the low 7 bits (opcode) give the group and, with it, the format; the other fields say which registers are involved and which constant (immediate) to use. RV32I has six formats (R, I, S, B, U and J) and all of them keep rs1, rs2 and rd in the same positions.

Worked example: 0x00500513

  1. Hexadecimal → binary. Each hex digit is 4 bits: 0x00500513 = 0000 0000 0101 0000 0000 0101 0001 0011.
  2. opcode = bits 6–0. 0010011: the OP-IMM group (operation with an immediate). This fixes the format: I.
  3. rd = bits 11–7. 01010 = 10 → x10, called a0 in the ABI. It is the destination register.
  4. funct3 = bits 14–12. 000: within OP-IMM, 000 is addi.
  5. rs1 = bits 19–15. 00000 = x0 (zero), the register that always holds 0.
  6. imm = bits 31–20. 000000000101 = 5. Bit 31 is 0, so the value is positive.
  7. Instruction. addi a0, zero, 5: a0 = 0 + 5. It is the encoding of the li a0, 5 pseudo-instruction.

The same breakdown, computed by the site’s decoder:

0x00500513 · I-Type
FieldBitsBinaryMeaning
imm[11:0][31:20]000000000101piece of the immediate
rs1[19:15]00000register x0 (zero)
funct3[14:12]000selects the operation within the group
rd[11:7]01010register x10 (a0)
opcode[6:0]0010011group OP-IMM
imm5 (0x5)rebuilt immediate (signed)
Instructionaddi a0, zero, 5

Notice the order of work: opcode first, because until you know the format you do not know how to read bits 31–7. In the I format those bits are a 12-bit immediate; in the R format they would be funct7 and rs2.

Decoder

Type an 8-digit hexadecimal word (with or without 0x) or a one-line assembly instruction. The colours of the bit grid match the fields of the detected format.

Guided exercise

Now an R-format instruction. Follow the same order: opcode first, then the other fields. When you check your answer you will see the full breakdown.

Decode an R-type instruction

Identify the fields of 0x40B50533. Pay attention to funct7: it is what tells add and sub apart.

0x40B50533

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Decode an instruction with a negative immediate

Convert 0xFFF28293 to binary and split it into fields. Give the format, the opcode, the registers, funct3 and the decimal value of the immediate.

0xFFF28293

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What the algorithm does exactly

  1. Converts the 8 hexadecimal digits into a 32-bit integer.
  2. Extracts the fields with shifts and masks: opcode = w & 0x7F, rd = (w >> 7) & 0x1F, funct3 = (w >> 12) & 0x7, rs1 = (w >> 15) & 0x1F, rs2 = (w >> 20) & 0x1F, funct7 = w >>> 25.
  3. Chooses the format from the opcode and reassembles the immediate from its pieces. The arithmetic right shift copies bit 31, which is the sign extension.
  4. Checks funct3 and funct7. If the combination is not an RV32I instruction (for example funct7 = 0000001, used by the M extension for mul), the word is reported as unrecognized instead of showing a wrong instruction.
  5. In assembly mode it goes the other way (fields → word) and then decodes the resulting word, so you always see both representations.

Scope and limitations

  • It recognizes 37 of the 40 RV32I instructions: add, sub, sll, slt, sltu, xor, srl, sra, or, and; addi, slti, sltiu, xori, ori, andi, slli, srli, srai; lb, lh, lw, lbu, lhu; sb, sh, sw; beq, bne, blt, bge, bltu, bgeu; jal, jalr, lui and auipc.
  • It does not recognize FENCE, ECALL or EBREAK, nor instructions from extensions (M, A, F, D, C) or RV64.
  • The assembler works on a single line and accepts neither labels nor pseudo-instructions (li, mv, j…): branches are written with the byte offset, for example beq t0, t1, -8.
  • For lui and auipc the immediate is written and shown as the 20-bit value (lui t0, 0x12345), not shifted by 12.
  • Branch offsets are shown as PC-relative numbers, not as labels.

Next

GuideHow to decode an RV32I instructionThe six formats, with one example each and how S, B and J immediates are rebuilt.ExerciseIdentify the format from the opcodeSix words, six formats.

References